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PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) FEATURES
* * 100MHz to 200MHz Fundamental Mode Crystal. Output range: 100 - 200MHz (no multiplication), 200 - 400MHz (2x multiplier), 400 - 800MHz (4x multiplier), or 800MHz - 1GHz (PLL520-09 TSSOP only, 8x multiplier). High yield design supports up to 2pF stray capacitance at 200MHz. CMOS (Standard drive PLL520-07 or Selectable Drive PLL520-06), PECL (Enable low PLL520-08 or Enable high PLL520-05) or LVDS output (PLL520-09). Integrated variable capacitors. Supports 3.3V-Power Supply. Available in 16-Pin (TSSOP or 3x3mm QFN) Note: PLL520-06 only available in 3x3mm. Note: PLL520-07 only available in TSSOP.
PIN CONFIGURATION (Top View)
VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND
PLL 520-0x
* *
* * *
GND/DRIVSEL*
SEL0^
10
GND
GND
BLOCK DIAGRAM
SEL OE VCON Oscillator XIN XOUT
Amplifier w/ integrated varicaps PLL (Phase Locked Loop)
^: Internal pull-up *: PLL520-06 pin 12 is output drive select (DRIVSEL) (0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
Part #
PLL520-08 PLL520-05 PLL520-06 PLL520-07 PLL520-09
OE State
Q Q
0 (Default) 1 0 1 (Default)
VCON
Output enabled Tri-state Tri-state Output enabled
PLL by-pass
OE input: Logical states defined by PECL levels for PLL520-08 Logical states defined by CMOS levels for PLL520-05/-06/07/-09
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 1
GND
The PLL520-05/-06/-07/-08/-09 is a family of VCXO ICs specifically designed to pull high frequency fundamental crystals. Their design was optimized to tolerate higher limits of interelectrode capacitance and bonding capacitance to improve yield. They achieve very low current into the crystal resulting in better overall stability. Their internal varicaps allow an on chip frequency pulling, controlled by the VCON input.
XIN XOUT SEL2^ OE
12 13 14 15 16 1
VDD
DESCRIPTION
11
SEL1^
9
8 7 6 5
GND CLKC VDD CLKT
P520-0x
2 3 4
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) PIN DESCRIPTIONS
Name
XIN XOUT OE VCON GND DRIVSEL**
TSSOP* Pin number
2 3 6 7 8,9, 10, 14 -
3x3mm QFN* Pin number
13 14 16 1 2,3,4,8,12 12
Type
I I I I P I
Description
Crystal in connector. Crystal out connector. Output enable pin. Frequency control input (0.3V to 3.0V) Ground (except pin 12 on PLL520-06: DRIVSEL see below). PLL520-06 only: Drive Select Input. This pin has an internal pull-up that will default DRIVSEL to `1' when not connect to GND. CMOS output of PLL520-06 will be high drive CMOS when DRIVSEL is set to `0', and will be standard CMOS otherwise. True output PECL (PLL520-08) or LVDS (PLL520-09) (N/C for PLL520-07) Complementary output PECL (PLL520-08) or LVDS (PLL520-09) (CMOS out for PLL520-07). Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V power supply.
CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD
11 13 16 15 5 4 1, 12
5 7 10 9 15 Not available 6,11
O O I I I I P
* Note: PLL520-06 only available in 3x3mm QFN, PLL520-07 only available in TSSOP. ** Note: DRIVSEL on pin 12 on PLL520-06 only.
FREQUENCY SELECTION TABLE
SEL3* SEL2 SEL1 SEL0 Selected Multiplier
0* 1* 1* 1*
0 0 1 1
1 1 1 1
1 1 0 1
Fin x 8 (PLL520-09 in TSSOP only) Fin x 4 Fin x 2 No multiplication
Note *: SEL3 is not available (always "1") in 3x3mm package All pins have internal pull-ups (default value is 1). Connect to GND to set to 0.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 2
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Crystal Specifications PARAMETERS
Crystal Resonator Frequency Crystal Loading Rating Interelectrode Capacitance Crystal Pullability Recommended ESR
SYMBOL
FXIN CL (xtal) C0 C0/C1 (xtal) RE
CONDITIONS
Parallel Fundamental Mode Die at VCON = 1.65V AT cut AT cut
MIN.
100 4
MAX.
200 3.5 250 30
UNITS
MHz pF pF
3. Voltage Controlled Crystal Oscillator PARAMETERS
VCXO Stabilization Time * VCXO Tuning Range CLK output pullability On-chip Varicaps control range Linearity VCXO Tuning Characteristic VCON input impedance VCON modulation BW
SYMBOL
TVCXOSTB
CONDITIONS
From power valid FXIN = 100 - 200MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V VCON = 0 to 3.3V
MIN.
TYP.
MAX.
10
UNITS
ms ppm ppm pF % ppm/V k kHz
200* 100* 4 - 18* 10* 65 60
0V VCON 3.3V, -3dB
25
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 3
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
4. General Electrical Specifications PARAMETERS
Supply Current (Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current
SYMBOL
IDD VDD
CONDITIONS
PECL/LVDS/CMOS @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD - 1.3V (PECL)
MIN.
TYP.
MAX.
100/80/40
UNITS
mA V % mA
2.97 45 45 45
50 50 50 50
3.63 55 55 55
5. Jitter Specifications PARAMETERS
Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 155MHz Period jitter RMS Period jitter peak-to-peak Accumulated jitter RMS Accumulated jitter peak-to-peak Random Jitter Integrated jitter RMS at 622MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 155.52MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz At 622.08MHz, with capacitive decoupling between VDD and GND. Over 10,000 cycles At 622.08MHz, with capacitive decoupling between VDD and GND. Over 1,000,000 cycles. "RJ" measured on Wavecrest SIA 3000 Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5 18.5 2.5 24 2.5 0.3 11 45 11 24 3 1.6
MAX.
20 27 0.4 49 27 1.8
UNITS
ps ps ps ps ps ps ps ps
6. Phase Noise Specifications PARAMETERS
Phase Noise relative to carrier
FREQUENCY
155.52MHz 622.08MHz
@10Hz
-75 -75
@100Hz
-95 -95
@1kHz
-125 -110
@10kHz
-140 -125
@100kHz
-145 -120
UNITS
dBc/Hz
Note: Phase Noise measured at VCON = 0V
7. CMOS Electrical Specifications PARAMETERS
Output drive current (High Drive) Output drive current (Standard Drive) Output Clock Rise/Fall Time (Standard Drive) Output Clock Rise/Fall Time (High Drive)
SYMBOL
IOH IOL IOH IOL
CONDITIONS
VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load 0.3V ~ 3.0V with 15 pF load
MIN.
30 30 10 10
TYP.
MAX.
UNITS
mA mA mA mA
2.4 1.2
ns
* Note: High Drive CMOS is available on PLL520-06 through DRIVSEL selector input on pin 12.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 4
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
8. LVDS Electrical Characteristics PARAMETERS
Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current
SYMBOL
VOD VOD VOH VOL VOS VOS IOXD IOSD
CONDITIONS
MIN.
247 -50
TYP.
355 1.4 1.1 1.2 3 1 -5.7
MAX.
454 50 1.6 1.375 25 10 -8
UNITS
mV mV V V V mV uA mA
RL = 100 (see figure)
0.9 1.125 0
Vout = VDD or GND VDD = 0V
9. LVDS Switching Characteristics PARAMETERS
Differential Clock Rise Time Differential Clock Fall Time
LVDS Levels Test Circuit
OUT
SYMBOL
tr tf
CONDITIONS
RL = 100 CL = 10 pF (see figure)
MIN.
0.2 0.2
TYP.
0.7 0.7
MAX.
1.0 1.0
UNITS
ns ns
LVDS Switching Test Circuit
OUT
50
CL = 10pF
VOD
VOS
VDIFF
RL = 100
50 CL = 10pF OUT OUT
LVDS Transistion Time Waveform
OUT 0V (Differential) OUT
80% VDIFF 20% 0V
80%
20%
tR
tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 5
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
10. PECL Electrical Characteristics PARAMETERS
Output High Voltage Output Low Voltage
SYMBOL
VOH VOL
CONDITIONS
RL = 50 to (VDD - 2V) (see figure)
MIN.
VDD - 1.025
MAX.
VDD - 1.620
UNITS
V V
11. PECL Switching Characteristics PARAMETERS
Clock Rise Time Clock Fall Time
SYMBOL
tr tf
CONDITIONS
@20/80% - PECL @80/20% - PECL
MIN.
TYP.
0.6 0.5
MAX.
1.5 1.5
UNITS
ns ns
PECL Levels Test Circuit
OUT VDD OUT
PECL Output Skew
50
2.0V 50%
50 OUT OUT tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
OUT 80% 50% 20% OUT tR tF
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PACKAGE INFORMATION
16 PIN TSSOP ( m m )
Sym bol A A1 B C D E H L e M in. M ax. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H
D
A A1 e B C L
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 7
PLL520-05/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal) ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL520-0x O C
PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL
PACKAGE TYPE O=TSSOP Q=QFN
Order Number PLL520-05OC PLL520-05OC-R PLL520-05QC PLL520-05QC-R PLL520-06QC PLL520-06QC-R PLL520-07OC PLL520-07OC-R PLL520-08OC PLL520-08OC-R PLL520-08QC PLL520-08QC-R PLL520-09OC PLL520-09OC-R PLL520-09QC PLL520-09QC-R
Marking P520-05OC P520-05OC P520-05QC P520-05QC P520-06QC P520-06QC P520-07OC P520-07OC P520-08OC P520-08OC P520-08QC P520-08QC P520-09OC P520-09OC P520-09QC P520-09QC
Package Option 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel)
16-Pin 3x3 QFN (Tube) 16-Pin 3x3 QFN (Tape and Reel) 16-Pin TSSOP (Tube) 16-Pin TSSOP (Tape and Reel) 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel)
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 8

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